In the construction of semiconductor chip package assemblies, it has been found desirable to interpose encapsulant material or an underfill between and/or around elements of semiconductor packages in an effort to reduce and/or redistribute the strain and stress on the connections between the semiconductor chip and a supporting circuitized substrate or dielectric element during operation of the chip, and to seal the elements against corrosion, as well as to insure intimate contact between the encapsulant, the semiconductor die and the other elements of the chip package.
Various methods have been devised to encapsulate semiconductor chip package assemblies and the like. Nevertheless, despite all of the effort which has been devoted to development of microelectronic encapsulation techniques, there are unmet needs for further improvements.